Code translation system

ABSTRACT

A system for translating a 12-bit per byte digital code into an 8-bit per byte code so that the latter may be transmitted on 8bit binary lines. The system is used to translate information electronically from a standard punched-hole card, which is normally in a 12-row, 80-column format, into an extended binarycoded decimal interchange code that can be more easily transmitted between computer channels and other devices such as card readers and punches.

United States Patent John V. McMillin lnventor [56] References Cited UNITED STATES PATENTS 223 3,422,221 l/ 1969 Sourgens 178/26 3,000,556 9/1961 Bewley et al.. 235/ 154X Patented May 1971 3 026 034 3/1962 Couleur 235/155 Ass'gnee wesunghme Leamngcmmmn 3:210:73s 10/1965 Duke et a1. 235/61.6X

Primary Examiner-Thomas A. Robinson Assistant Examiner-Michael K. Wolensky Attorneys-Haven E. Simmons and James C. Nemmers CODE TRANSLATION SYSTEM ABSTRACT A S ystem for translating a 12 bit per byte dlgital l1 Chums l7 Drawmg Flgs' code into an 8-bit per byte code so that the latter may be US. Cl 340/347DD, transmitted on 8-bit binary lines. The system is used to trans- 178/ 26A, 340/1725 late information electronically from a standard punched-hole Int. Cl H03k 13/24, card, which is normally in a l2-row, 80-column format, into H04i 3/00, G06f 5/02 an extended binary-coded decimal interchange code that can Field ofSearch 340/347 be more easily transmitted between computer channels and (DD), 172.5; 235/6l.6, 154, 155; 178/26, 26 (A) other devices such as card readers and punches.

PUNCHED INPUT HOLE COMMAND INPUT SIGNALS SIGNALS INPUT REsIsTER ZONE LINES DATA ZONE INTERMEDIATE MODIFIER MODE DECODER UNIT DECODER MODIFIER NUMERIC (ZONE) LINES LOW OUTPUT ORDER BYTE MODIFIER TRANSLATOR LOW HIGH ORDER ORDER REGISTER l l REGISTER 8 BIT OUTPUT BYTE minnow 4m saw 010 1o INPUT COMMAND SIGNALS PUNCHED HOLE INPUT SIGNALS v 1 zone v MODIFIER NUMERIC LINES DATA MODE *2 UNIT INPUT REGISTER ZONE LINES INTERMEDIATE DECODER ZONE DECODER UNIT oscooea MODIFIER (ZONE) LOW ORDER MODIFIER LOW ORDER OUTPUT BYTE TRANSLATOR HIGH ORDER REGISTER I FIG I REGISTER 8 BIT OUTPUT BYTE INVIiN'IOR.

JOHN v. MCMI-LLVIN ATTORNEY EPATENTJEDHAY 4:91: E 3577.142

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JOHN v. MCMILLIN ATTORNEY PATENTED-MAY 4m I I 'v f 557K142 sum 03 or 10 puucnm HOLE INPUT CHARACTERS ou*2 000 a EVEN was CLOCK CLOCK- PRESET no PUNCH smus a PRESET N0 PUNCH STATUS DH 2 000 DN E 000 SIROBE 0M 2 EVEN STROBE' DH 2 EVEN STROBE on I smoae D" l STROBE FIG 2h INVENTOR. JOHN V. M MILLIN ATTORNEY FIG" 2a PATENIEUMAY 4197:

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INVENTOR.

JOHN v. MCMILLIN ATTORNEY PATE'NIEDMAY 4197a Y 3571142 sum as 0F10 INVENTOR.

. JOHN v. MGMILLIN FIG 2d ATTORNEY PATE'NTED'H'AY 4m 3571.142 saw near 10;

. 0PT BYTES BIT POSITION 0-3 11F l6 HEXADECIMAL LINES INVENTOR.

JOHN v. MCM'ILLIN ATTORNEY FIG' 2f PATAIE'NTEDHAY 419m 3577.142

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V m oi INVENI'OR. JOHN v MCMILLIN E0 uZE ATTORNEY EBCDIC SBit code TABLE #lContinued CODE TRANSLATION SYSTEM BACKGROUND OF THE INVENTION In digital computers and data processing systems number system is used almost exclusively because of its suitability to electronic computing techniques and ease of trans- Hexa- Punched decimal card code Decimal No punches 12-0-9-1 12-0-9-2 12-0-9-3 -12O94 12-0-9-5 12-0-9-6 120-97 the binary mission. There are known in the prior art a number of translating or conversion systems for accomplishing conversion from one or the other of the various codes used in digital computers and data processing systems. Cards containing punched holes have been known and used for many years in data processing systems. The format of the standard punched-hole card is normally 12 rows and 80 columns of data bits. The cards are typically read by an electronic card reader on a column-bycolumn basis producing a 12-bit byte for transmission. If vall mmwwMwwww 5 2 1m 7 6 6 m m C 5 H i B 4 w or m w 3 X D 2 66 0 mm m 1 mu .0 lb 8 dm d. m D E. M0 em .L C0 M H nm E Av 8 iw T PC n .m .m m m m d em 0 e mw S d 8e 1 m m En 6 mm m HHHHMMH TABLE #I Continued Punched card code In order to transmit the l2-bit punched-hole column bytes to the more suitable 8-line l/O channel commonly used in computers and data processing systems, it is thus necessary to translate the 12-bit punched-hole pattern code into the 8-bit code. This invention accomplishes this function with a great reduction in the number of components and interconnections than was possible with prior art code conversion systems, thus resulting in a drastic reduction in cost and an increase in reliability of the system.

SUMMARY OF THE INVENTION The conversion system of the invention receives and stores the signals received as the punched-holes on the tabulating card are read. The signals are then read out of storage by appropriate command signals. When read out, the l2-input bits are divided into a zone field and a numeric" field. The zone field, containing 4 bits, is translated into an 8-line output which in turn is decoded into a hexadecimal code. The system of the invention also provides for modification of the zone signals to take care of irregularities in the EBCDIC 18-bit byte translation. Once thus decoded and modified, the zone signals, now in a l6-line hexadecimal coded output, are translated into a 4-bit output signal which forms half of the final 8-bit byte output pattern. The numeric field of 8 bits is read out of the input register and translated into a 4-bit pattern which forms the other half of the 8-bit output byte.

There are also some situations in which it is desirable to transmit punched-hole patterns other than the 256 valid combinations defined by the EBCDIC translation code. Inasmuch as there is one byte of data for each l2-bit punched-hole card column, it is not possible to transmit the entire 12-bit byte at one time since only eight lines are required for the 8-bit EBC- DIC code. However, with the converter of the invention, it is possible to transmit the l2-bit punched-hole pattern by splitting it into two 6-bit bytes.

BRIEF DESCRIPTION OF THE DRAWINGS The objects, features and advantages of the invention will become readily apparent from a description of the preferred embodiment herein taken in connection with the drawings in which:

FIG. 1 is a block diagram illustrating the various basic phases of a system employing the principles of the invention;

FIGS. 2a through 2h assembled together as shown by FIG. 2, are a circuit diagram representing the electrical circuit arrangement of the converter; and

FIGS. 3a through 3g represent the elementary circuits used in the converter and their conventional representation in the circuit diagrams of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT As previously indicated, data recorded on standard punched-hole cards is normally in a l2-row SO-column format, although sometimes 5 l-column or other card lengths are used. The cards are typically read on a column-by-column basis, each column containing, of course, 12 possible punching positions or rows. The information thus read from the 12 rows of each column is transmitted on 12 lines into a l2-bit input register indicated in FIG. 1 by the reference latter A and shown in detail in FIG. 2a. The input register A is capable of storing the bytes of data until read out upon receipt of an appropriate command signal. In FIG. 1, there are represented the I2-input lines containing the information transmitted from the card reader or other source, and also represented are lines upon which command signals from an appropriate command source (not shown) will be received by the input register A.

Data Mode 01 The 12 punched-hole positions or rows on the standard punched-hole card are defined as the l2, l1, 0, I, 2, 3, 4, 5, 6, 7, 8, and 9 positions with the sequence being from the top to the bottom of the card, respectively. In what is referred to hereinafter as Data Mode 0l transmission (DM01), the 12, 11 and 0 positions, which are located on the top portion of the card column, together with the 9 position, located on the bottom of the column, constitute what is referred to as the zone field. The remaining punched positions 1 through 8 inclusive are referred to as the numeric field. In the extended binary coded decimal interchange code (EBCDIC), all 16 possible combinations of the zone positions are used and are assigned to the zone decode numbers according to the following table:

TABLE #2 Binary status Zone decode No.

Zone punch pattern Hex code ble and the right character represents the low-order or 47 nibble. For example, A7 in the hexadecimal code represents 1010 0111 in the EBCDIC 8-bit code. (See Table 01). Thus, the hexadecimalcode, with ranges from 00 to FF, corresponds =to the 256 binary states of the EBCDIC 8-bit code from 0000 0000 to 1111 111 1..

Zone Field With reference now to the punch positions comprising the zone field, an intermediate decoder B (FIG. 2b) receives signals from the four positions 12, ll, 0, 9 on eight separate lines which are represented by a single line in FIG. 1. Intermediate decoder B translates the 12, 11, 0, 9 signals into an 8 line output for input to the zone decoder Unit C (FIG. 2b). 115525 d eEEdEFCErEns Ia tes the 8-line input code into one of the 16 hexadecimal code signals for input to a group of 51 zone gates, which group is referred to in FIG. 1 as the decoder modifier group D (DMZ-group See FIGS. 2d and 22).

A study of the code translation table has shown that five Boolean statements (hereinafter referred to as modifiers) are needed in addition to the zone field decoding in order to cover all the permissible 256 EBCDIC characters. The complements or logic negation of these modifiers are also required. The following table illustrates the punch patterns for the various modifier statements, the digit shown referring to punched-hole positions (e.g., 6 means punched-hole position 6 is present in a given column of the punched-hole card):

TABLE #3.-BOOLEAN EQUATIONS FOR MODIFIER LINES Punch pattern for TABLE 3. BOOLEAN EQUATIONS FOR MODIFIER LINES Continued Punch pattern for A zone modifier unit E (FIG. 20) accepts signals from the input register A and modifies them in accordance with the modifier statement shown in the foregoing Table 03. The outputs of the zone modifier unit E are transmitted to the gates of DMZ-group D and are used in conjunction with the output signals from the zone decoder Unit C to handle any irregularity in the translation. A study of the translation table, Table 01, will reveal that while some of the required conversions are repetitive binary sequences, there are a number of irregularities in the translations. The 16 output lines from the zone decoder Unit C and the 10 output lines from the zone modifier Unit E (which l0 lines represent the five modifier statements and their complements) are NAND-detected in the DMZ-group D. From the 5.1 gates of the DMZ-group D, there are 34 final outputs which correspond to inputs from the zone modifier Unit E and zone decoder C according to the following table, the references being to the indicated numerals and letters of FIGS. 2d and 2e:

TABLE #4 EB CDIC punch character DMZ group decimal notation gate No.

Modifier input Zone Input newe e dzzppwwiowzwiowwprowzm :1

It should be noted that the sequence of the 51 gates in the DMZ-group D are identified by number for purposes of identification only, these numbers having no logic-function relationship to any of the other codes.

It should be noted from the foregoing Table 04 that each of the gates in the DMZ-group D has one zone input from the zone decoder C and from one to three inputs from the zone modifier Unit E. Nineteen of the DMZ-group D gates have multiple inputs from the zone modifier E while the other 32 gates DMZ-group D have only one such input. The output of 'any gate of the DMX-group D is logic only when all of its inputs are logic 1.

By using the following table, the output state of any of the gates in the DMZ-group D may be readily determined. In using the table, it must be recognized that the given input from the zone decoder Unit C must also be present for decoding to actually occur. An X in the table indicates that the modifier function is logic I when the given punch pattern is present (e.g., modifier A is logic 1 only when the 8-2 punch pattern exists):

TABLE #5 With reference to the low-order or 4-7 nibble, there are three groups of the EBCDlC characters in which the standard numeric field pattern to 4-bit binary code translation, as shown in Table 06 above, must be modified. The first of these three groups is referred to as the LOAD-9 group which includes the conversion shown in decimal line numbers 137, 153,169,185, 201, 217, 233 and 249 ofTable 01. In the standard numeric to 4-bit low-order nibble translation, Table 06, a numeric 81 is translated into hex-9 of the low-order nibble. In the EBCDlC group, however, a high-order hex-9 must be translated even though an 81 punch combination is not Punches present The 34 output lines from the gates of the DMZ-group D are translated by the output byte translator F (FIG. 2]) into one out of the 16 hexadecimal characters representing the 0-3 or high'order nibble. The 16-line output of the translator F is accepted by the final high-order register G (FIG. 2g) which converts the hexadecimal code into a 4-bit output signal that forms the high-order nibble of the 8-bit byte output pattern.

Numeric Field As previously indicated, the numeric field ranges from a 1 punch position to an 8 punch position. The following table shows the permitted combinations within the numeric field:

TABLE #6 Binary weight in the 4-7 output nibble Zone Numeric Decode No. field punches Hex Zone No. 0... Blank 1 Zone No. 1... Repeat Zone No. 2 Repeat 2 Zone No. 15.. Repeat 2 Repeat- Repeat.

16 Zone X 16 patterns/zone =256 EBCDIC CHAR.

The numeric signals from the input register A are thus received by the low-order final register H(FIG. 2g) which converts them into a 4-bit pattern that forms the low-order nibble of the 8-bit output byte.

present. This can be illustrated by the example of decimal 137 of the EBCDlC translation table, Table 01. On the EBCDlC translation Table 01, decimal 137 is represented by the l2-- 09 punch combination which, according to the standard translation table of Table 06, means that the numeric field pattern is blank and the low-order nibble output should be binary 0000 or hex-0. In the EBCDlC table, Table 01, decimal 137, however, shows that the low-order nibble binary code 1001 or hex-9. When punch pattern 12-0-9 is present, the output from gate 44 of the DMZ-group D decodes the decimal 137. Thus, the output of gate 44 of the DMZ-group D is used to modify the low-order nibble translation matrix from a hex-0 to a hex-9. This is accomplished by the low-order modifying unit J (FIG. 2f) of FIG. 1. The following table shows the LOAD-9 group EBCDIC decimal numbers which are modified by the low-order modifier using the outputs from the indicated gates of the DMZ-group D:

TABLE #7 DMZ gate Decimal line No.: No.

What is referred to as the LOAD-10 group involves only decimal 106. Decimal 106 is modified by using the output from gate 15 of the DMZ-group D.

The third group is referred to as the INHIBIT group. The standard 4-7 low-order nibble translation table, Table 06 shows that an 8-1 punch position read from a card is translated into a binary 1001 or hex-9. However, certain punch patterns in the EBCDlC code containing an 8---] punch position require a low-order nibble binary output of 0000 or hex-0. For example, decimal 128 on the EBCDlC translation table, Table 01, results from a l2081 punch pattern, requiring a hex0 for the low-order nibble. In order to correct this, in this example, an output line from the DMZ-group D corresponding to decimal 128 is used to INHIBIT the hex-9 that would normally be encoded into the low-order nibble out put lines. The following table indicates the decimal lines requiring the INHIBIT-function from the outputs of the corresponding gates of the DMZ-group D:

mitted; 80 for DM01, 80 for DM02 ODD and finally 80 for DM02 EVEN. In FIG. 1, the group of gates designated as DM02 unit K (FIGS. 20 and 2h) accepts the l2-line punched- TABLE #8 hole pattern signals from the 12-bit input register A, and DMZ under control of the ODD-EVEN command signals, transmit Decimal line No fi g alternating ODD and EVEN patterns of 6-bit signals to the high-order and low-order final output registers G and H. High- 0 1 order output register G accepts 2 bits of the DM02 signals g3 g from DM02 unit K to form part of the 6-bit DM02 output 7 10 byte. The lower order output byte register I-I accepts4 bits of 128 19 the DM02 signals to form part of the 6-b1t DM02 output byte. i3::::::::::::::::::::::::::::::::::: 2? r e p nandopenon i523I:33331313113331::::::::::::::: 5% Detailed cinnniny. for the convene of the invention Data M Ode 02 shown in the logic diagram of FIGS. 2a through 2h which are assembled as shown in FIG. 2 to form the complete circuit. There are some situations in which it is desirable or necessa- FIGS. 30 through 3g are details of the NAND logic elements ry to transmit punched-hole patterns other than the 25o valid used in the circuit of FIG. 2. Also, in the logic diagram, all combinations defined in the EBCDIC translation code, Table 20 wired-OR connections are enclosed by an AND symbol. This 0l.To distinguish between these two possible modes of operaapparent contradiction is explained by the fact that tradition, the EBCDIC mode of 256 combinations has been tionally, when so-called collector outputs were directly tied referred to as Data-Mode 01 or simply DM01. The other together, this procedure was given the logic name of collecmode wherein all 4,096 punch position combinations can be tOr-ORing" or wired-OR." However, in the case of collecconsidered valid, is defined as Data Mode 02 or more simply ing" 0f the outputs of DTL NAND logic elements, the DM02. Only eight lines are needed to transmit the 8-bit EBC- actual l gic p r tion performed is one of ANDing the in- DIC code. Therefore, it is not possible to send over these eight dividual NAND o tp t a m n l gi output. The c nlines the entire 12-bit punched-hole attern t one tim i ventional practice in defining such connections is wired-OR much as 12 li s ld b e i d, l-l if he d and this terminology will be used in the following description. column of l2-bits is split into two 6-bit bytes, these bytes can To aid in the tracing of signal flow through the various logic be transmitted over the eight lines. These bytes ar defin d as elements in the circuit of FIG. 2, active logic levels are shown the ODD and EVEN bytes and the terms DM02 ODD and at numerous points on the logic diagram, together with ap- DM02 EVEN" are used to refer to the tra i i d th propriate Boolean logic statements or other coded informadata contained in the ODD byte and EVEN byte, eti l tion. An active" logic level implies that the indicated logic The translation characteristics are shown in the following tatransition Will Occur ly if the stated Co ons a e acti e" ble: at the point of interest, and as such, may be either logic 1 or TABLE #9 Punch code Odd byte Punch code Even byte 12110123Bits 01-234567456789Bits-+01234567 000000 00000000000000 00000000 I12 111 Z0 Z1 12 I: 0 0 In In Z0 It I: 1:! Y4 Y5 Y0 Y1 Ya Yr 0 0 Y4 Y5 Y1 Y1 Ya Ya 111111 00111111111111 00111111 Nora: Symbols.-0"=Punch absent; z1=L0gic 0" or logic 1 lower group; "1"=Punch present.

It should be noted that when using either the ODD OR EVEN byte, the upper 2 bits, 0 and l, which are the first 2 bits of the high-order 0-3 nibble, are not used as only six iines are required for transmission of each byte of the 12-bit punchedhole pattern. The relationship between punched-hole row position and the ODD and EVEN output bytes is shown by the following table:

TABLE #10 9 X Bit positions of output byte- 0 1 2 3 4 5 6 7 The converter of this invention has provisions for reading out the DM02 information as well as DM01. It is possible to program the readout as DM01 only, DM02 only, or finally both modes for a given card column. This can be done by controlling which combination of commands are issued to the converter. In cases where both modes are programmed for a full 80-column card, a total of 240 output bytes will be transfor given punch in upper group; Y1=Logic 0" or logic 1 [or given punch in logic 0. In the logic diagram, logic 0 equals low-level voltage, while logic 1 equals high-level voltage. The symbol "T indicates logic I is the active level during strobe, while symbol l l indicates logic 0 is the active level during strobe. Also, the symbol l' indicates logic 1 is the active level after CLOCK input falls while the symbol indicates logic 0 is the active level.

The l2-line input to the input register A is stored upon command of an input CLOCK signal, and the stored data is held until the next CLOCK signal or until a reset signal is received. The DM01 8-bit output byte and/or the two 6-bit output ODD and EVEN bytes of DM02 are available upon command of the DM01 strobe, DM02 ODD or DM02 EVEN strobe inputs, respectively, The presence of a punch on a card is indicated by a logic 1, and the absence of a given punch by a logic 0 on the respective input line for the punch position. The logic complement of each of the 12 punched-hole input lines is generated by a single-input NAND inverter. The complemented signal output is connected to the K input of a JK binary element associated with each punched-hole input line, while the direct input is connected to the J input of the binary element. A CLOCK pulse on the C input to the J K element will, upon fall of the CLOCK, transfer the JK input logic levels to the outputs of the JK elements regardless of the previous logic state of these elements. By use of the J K elements in this self-resetting manner, it is not necessary to reset the JK units of the input register A prior to CLOCKing-in each new column of punched data, since a given pattern of punch signals, once CLOCKedin, will remain stored indefinitely until a new CLOCK comrnand is received. If it is desirable in a given situation to have all the J K elements of the input register reset to a no punches condition prior to arrival of the first CLOCK pulse, this may be effected by applying a PRESET pulse to the input register A. This pulse is transmitted to the P reset inputs of all JK elements.

The outputs of the JK elements from the zone field, the l2, l1, 0, and 9 punched-hole input lines, are connected in a matrix-decode manner to the inputs of the zone intermediate decoder B. The four possible combinations of the l21l punches and the four possible combinations of the -9 punches are decoded separately as shown in FIG. 2b. This permits the use of Z-input NAND elements throughout the zone intermediate decoder B rather than 4-input devices which would greatly increase the physical space required for the input lines. Only one line of each of the four output lines from the 12-11 and 0-9 decode groups of the decoder B will be active (logic 1) for any given punch pattern. Thus, after inversion by a following NAND stage, a logic 1 will appear on one of the output lines of each decode group.

The next operation in zone decoding is that performed by the zone decoder unit C, which is shown in detail in FIG. 2b. Sixteen 2-input NAND elements, followed by 16 NAND inverters, complete the zone decoding resulting in 16 output lines, only one of which will contain a logic 1 at any given time, the particular output line being determined by the zone input punch pattern, as defined in Table 02 of the Specification. The gates comprising the zone decoder unit C thus perform the 8-line input to l6-line output decoding. Since only one of the four outputs of each decoder group of the intermediate decoder B can be logic I for a given zone punch pattern, the final decoding by decoder unit C is performed by connecting these eight output lines in matrix-decode fashion to the 16 input lines of the unit C. Thus, each 2-input NAND element of decoder unit C has one input connected to one of the four output lines of the 12-l1 decode group of decoder B, while the other input line is connected to one of the four output lines in the 0-9 decode group of decoder B.

The 16 output lines from the final zone decoder unit C are connected to the inputs of the 51 gates of DMZ-group D. These gates and their input and output lines are shown in FIGS. 2d and 22. As previously indicated, each of the 51 gates of DMZ-group D decodes a unique combination of inputs from the zone decoder unit C and the zone modifier unit E, the decoded output of each gate of DMZ-group D being equivalent to one or more decimal characters of the 256 valid punch combinations. After all possible wired-ORing has taken place as shown, there are 34 output lines from the DMZ-group D that must be further reduced to 16 lines to represent the 16 hexadecimal code lines corresponding to the high-order nibble of the final 8-bit output byte. An output from a given gate of the DMZgroup D goes from logic 1 to logic 0 only when all of its respective inputs (both the ZONE line and MODIFIER inputs) are logic 1. However, within a group of gates whose outputs are wire-ORed together, any one of the gates within that group will force the common wire-OR output line to logic 0 when that gate has all logic I s on its input. Moreover, during correct operation, only one of the gates within the entire group of 51 gates will be decoding to a logic 0 level for a given punched-hole input code.

The final translation of the 34 outputs from the DMZrgroup D is performed by the output byte translator F shown in FIG. 2f. Since the active logic state of any of the 34 output lines from the DMZ-group D is logic 0, the 13 multiple-input NAND elements of the translator F can be considered as performing logic-ORing, then inverting of the logic 0 input signal. The other three single-input NAND elements of translator F simply invert the incoming logic 0 active-level signal to a logic l. An analysis of the logic for the various output lines from the DMZrgroup D gates as translated by translator F will result in the derivation of 16 groups of punched-hole codes, each group having a distinctive HEX code output for the high-order nibble translation. (Note that bit O is decoded but not used.)

There will be 16 punched-hole patterns or codes per group, and thus a total code count of 256-the complete EBCDIC set.

The 16 hexadecimal lines thus generated by the DMZ-group D gates and the gates of translator F must be reduced to a 4-bit code to represent the high-order nibble of the 8-bit output byte. The NAND logic elements for performing this final translation comprise the high-order register G and are shown in FIG. 2g. The active logic level at the 16 outputs from translator F is logic 1, and only one line out of the 16 will be active whenever a valid pattern has been clocked into the input register A. Four 8-input NAND gate elements could be used for the final conversion, but 4-input expander elements are used with 4-input expandable NAND gate elements. The hexadecimal to binary conversion is only a matter of the given hexadecimal line activating the proper inputs of the gates comprising the final high-order register G. Table 02 of the Specification shows the conversion from the HEX code to the binary status of the nibble.

As previously stated, modifiers are needed in conjunction with the zone field decoding to cover all 256 valid states of the EBCDIC code. The zone modifier E is shown in detail in FIG. 20. Although 10 modifier lines are required, five of them are the complements of the other five. The modifiers and their complements are shown in Table 03. Hardware-wise, it is immaterial whether the modifier functions or their complements are decoded, as the one not decoded is readily obtained by NAND-inverting the decoded function. The modifiers generated by the respective NAN D gates are indicated in FIG. 20. All 10 of the output lines from the zone modifier E are connected to corresponding inputs of the various gates of the DMZ-group D. Whenever there is any bit of the NUMERIC field punch-code clocked into the input register A, the modifier lines are actively decoding. A PRESET condition, equivalent to a BLANK in the NUMERIC field, will produce logic 1's on the B, D, P, R and T modifier output lines while the others will be at logic 0. See Table 05 of the Specification.

With reference now to decoding of the NUMERIC field, the low-order register 1-1 (see FIG. 2g) receives the l to 8 punches and generates an equivalent 4-bit binary pattern. The NAND- input wiring of the 1 to 8 punched input lines from the input register A output lines is in a matrix-encode pattern to result in the input-to-output translation shown in Table 06 of the Specification. The outputs from the input register A, which are active whenever a punch-pattern has been clocked-in to the JK elements of the input register, are pulse-gated into the low-order register H by the eight 2-input NAND elements shown in FIG. 2g. This occurs during the DMOI strobe pulse, and thus one input of each of the eight gates is connected to the punch-code Q outputs of the JK elements while the other input of each gate is bussed into a common line that is tied to the logic 1 active DM0l STROBE which in turn is ANDED with IHB. This means that a logic 0 active-level pulse will be generated by the output of any of these eight gates during DM0l STROBE time when the given NUMERIC field punch is present in the input register A. As previously explained, the INHIBIT action prevents certain irregular 8-1 punch combinations from encoding into a HEX-9. See Table 08.

Referring again to FIG. 2g, it is noted that 4-input expandable NAND-elements are required for the final low-order nibble encoding gates. A HEX-9, or binary 1001, must appear on the low-order nibble output lines for eight of the EBCDIC punch-codes not containing an 81 punch combination, the only NUMERIC code for which a 1001 output would normally be generated by the low-order nibble register H. Therefore, as shown in FIG. 2f (which illustrates the low-order modifier J) whenever any of these eight irregular codes are detected by the gates of the DMZ-group D, the ORed logic 1 output of these gates is NANDed with the DM0l STROBE pulse in the low-order modifier J. Also, when any of the irregular" codes are detected, the DM0l-gated LOAD-9 active-level logic 0 output signal is connected to an input on the binary-numeral 4 and binary-numeral 1 weight NAND gate of the low-order register H (SeeFIG. 2g). Thus, the required 1001 binary output code appears on the low-order nibble lines during a DM01 STROBE.

As previously indicated, another group of EBCDIC characters in which the 47 nibble must be modified, is the LOAD-10 group. The decimal 106, resulting from a 12- 11 punch, requires a low-order nibble output of binary 1010 or HEX-A. However, since the low-order nibble encoders would normally generate a binary 0000 on the output lines during DMl STROBE-time when no 1 to 8 NUMERIC punches were present, a HEX-A must be specially encoded in this situation. Gate 015 of the DMZ-group D detects the 12-11 punch codes, and its output is inverted and NANDed with the DM01 STROBE by modifier J. The output'from modifier .I is connnected to an input of the bina'ry-4'and binary-2 gates of the low-order nibble register H. Thus, the required 1010 binary output code appears on the output of the low-order register H during the DM01 STROBE.

The last group of EBCDIC characters in which the loworder nibble must be modified has already been referred to as the INHIBIT group. The presence of a l-punch plus an 8- punch NUMERIC field normally indicates that a binary 1001 code should be available on the low-order nibble output lines during the DM01 STROBE-time. However, nine of theEBC- DIC punch-codes containing an S-punch plus l-combination require a binary 0000 on the output lines of the low-order nibble during DM01 STROBE-time. These nine punch-codes are detected by the appropriate gates of the'DMZ-group D and the active logic 0 output of the gates and NAND ORed into a commonbus'sed signal by the gates of the low-order modifier J (See FIG. 2)). The INHIBITing function is performedby the NAND gates so designated in FIG. 20. Thus, when an IHB signal is present, the low-order encoding gates of the lowoi'der register H are, in effect, not even STROBED and the final output code will be 0000.

Validity detection of multiple punches in the lto 7-pun'ch group is performed by the NAND-elements as so indicat'ediri FIG. 20. Detection is done by the so-called ripple method, whereby the l-punch and 2-punch JK registers are tested for the presence of both punches, while thefp'resence of either-the l-punch or the Z pIunch is logic 1 rippled from one gate'to another and NANDED with the 3-punch logic lfrom the Q output of its J K storage element. Rippling to the next multiple-punch detect gate, etc., continues until all multiple-punch possibilities have been tested. Whenever logic 1 coincidence is detected between the previous rippled-OR output and a given punch, the corresponding NAND-gate goes to logic'O. Thus, all six of these miiltiple-punch coincidence gates are wire- ORed together into a common validity-bus logic 0 active-level output signal. Thissignal is inverted to a logic 1 active-level and NANDED with a logic 1 active-level DM01 STROBE- which is reinverted, and after routingto the diode and terrninal validity line (see FIG. 23) becomes the validity error output signal and isavailable for external-circuit sampling-at any time the 8-bit outpittbyte is sampled-in theDMOl mode.

Gating of the ODDaffd EVEN bytes for DM02 operation is performed by the DM02'unit K, part of which is shown in FIG.

2a and part in FIG. 2h. Referring first to FIG. 2a, six Z-input' panders are connected to the expander inputs of the 2 and 3 bit-position output encoders of the high ofder register G (See FIG. 23). The other outputs of the expanders are connectedto the inputs of all four encoders in the low-order nibble register H (See FIG. 2g).

The output of the converter is available only when the DM01 input STROBE is active. Reference to the logic diagram of FIG. 2 shows that provisions are made to accept either a logic 1 or logic 0 active-level for the DM01 input STROBE.

In normal use, a 12-bit punched-hole pattern is presented to the input register A, the data is stored during the CLOCK pulse, and the 8-bit EBCDIC byte is then STROBED out via the input STROBE pulse. At all other times, the eight output lines will remain at logic 0. As well as the eight direct output lines, eight diode output lines (see FIG. 2g) are available for convenient ORing into other data transmission busses. In

order to provide the external circuitry which accepts the 8-bit output byte, an indication of when these eight lines may be sampled for valid data is available from the converter on a delayed STROBE output line (See FIG. 2g).

Summary As stated previously, only 256 punch combinations out of the total possible 4,096 combinations of a given card column are valid EBCDIC combinations. The 16 zone-field combinations using punch positions 12, 11, 0 and 9 are shownin Table 02. The 16 valid numeric field punched position combinations are listed in Table 06. A blank column, or EBCDIC decimal 64, is, of course, the EBCDIC character represented by the least number of punches (none) and decimal lines 48 and 250 to 255 represent the most heavily punched columns, any column of this group containing six punches. Each incoming l2-bit punch pattern to be translated into EBCDIC code is checked for validity to verify that the pattern represents one of the 256 valid codes. The circuitry of the converter is wired to detect the presence of more than one punch in the numeric field.

Many types of logic can be used to implement the function of the converter. However, from a design-economy standpoint, thelogic operation internally performed within the converter of' the invention results in a minimum number of logic elements to actually perform the required translation. An ideal approach would be one that requires the least number of logic elements all of one type and of the smallest size and lowest cost. The converter of the invention'utilizes these factors to a maximum, resulting in a converter that uses only low cost logic elements and a minimum number of them. It will be obvious to those skilled in the art that variations and modifications can be made to the preferred embodiment disclosed herein without departing from the spirit and scope of the invention. It is my intention, however, that all such revisions and modifications will be included within the scope of the following claims.

I claim:

1. A code translation system for converting a first multibitper-byte digital code into a second digital code in which each byte contains a fewer number of bits than said first code, said system comprising, input storage means adapted to receive and store successive multibit input bytes of a first code in which combinations of bits within each byte represent items of coded information, command means for reading out each entire input byte from said input storage means at selected times prior to entry of the next succeeding multibit input byte into said input storage means, means for dividing: each input'byte into two groups of bits when each input byte is readout by said command means, and means responsive to read out of said groups of bits by said command means for translating each group of bits into an output byte of a second code containing fewer bits per byte than the input byte of said first code from which said output byte was converted.

2. The code translation system of claim 1 in which said means for dividing said input byte into two groups'of bits divides said byte in groups' containing an equal number of bits, and command means is provided for transmitting said groups into an output byte in alternating patterns.

3. The code translation system of claim 1 in which said input byte of said firstcode contains l2 bits, and said input byte is divided intotwo groups of bits, a firstgroup containing 8 bits of the l2-bit input-byte, a second group containing 4 bits of the 12-bit input byte, said firstgroup being'translat'ed into a 4- bit output nibble, and said'second group being, translated into a4 -bit output nibble.

4. The code translation system of claim 3 in which the translation of said first and second groups takes place substantially simultaneously, and said nibbles thereby form an 8-bit output byte, the bits of which can be transmitted from said system simultaneously.

5. The code translation system of claim 3 in which there are selected 256 valid patterns of the possible combinations of bits of the byte of said first code, which 256 patterns define the permissible characters of said second code, and validity detection means is provided in connection with said input storage means to detect combinations in each input byte other than said 256 valid combinations.

6. The code translation system of claim 5 in which 7 selected bits of said first group of 8 bits of an input byte there can be only 1 valid bit in each byte, and said validity detection means will detect the presence of more than 1 such bit in a byte.

7. The code translation system of claim 5 in which there is provided intermediate decoder means responsive to an output from said input storage means to translate each of the 4 bits of said second group of the input byte into one of i6 hexadecimal code bits, and means responsive to an output from said intermediate decoder means to translate said 16 hexadecimal code bits into the 4-bit output nibble.

8. The code translation system of claim 7 in which in 7 selected bits of said first group of 8 bits of an input byte, there can be only 1 valid bit in each byte, and means is provided to detect the presence of more than 1 such bit in a byte.

9. The code translation system of claim 8 in which modifying means is provided responsive to the outputs of each group of bits read out from said input storage means to modify certain of said outputs in order to make the proper conversion from the first code to the second code.

10. A method of converting from a first l2-bit-per-byte l digital code representing items of coded data into a second code having in each byte 8 bits, said method comprising: storing each byte of data coded according to said first code; reading out each entire byte from storage by predetermined signals prior to entry of the next succeeding multibit input byte into said input storage means; dividing the output from storage of each said first code byte into two groups of bits, one group containing 8 bits and the other group 4 bits; separately trans- 0 lating the bits of each said group into a 4-bit nibble; and form- 

1. A code translation system for converting a first multibitper-byte digital code into a second digital code in which each byte contains a fewer number of bits than said first code, said system comprising, input storage means adapted to receive and store successive multibit input bytes of a first code in which combinations of bits within each byte represent items of coded information, command means for reading out each entire input byte from said input storage means at selected times prior to entry of the next succeeding multibit input byte into said input storage means, means for dividing each input byte into two groups of bits when each input byte is read out by said command means, and means responsive to read out of said groups of bits by said command means for translating each group of bits into an output byte of a second code containing fewer bits per byte than the input byte of said first code from which said output byte was converted.
 2. The code translation system of claim 1 in which said means for dividing said input byte into two groups of bits divides said byTe in groups containing an equal number of bits, and command means is provided for transmitting said groups into an output byte in alternating patterns.
 3. The code translation system of claim 1 in which said input byte of said first code contains 12 bits, and said input byte is divided into two groups of bits, a first group containing 8 bits of the 12-bit input byte, a second group containing 4 bits of the 12-bit input byte, said first group being translated into a 4-bit output nibble, and said second group being translated into a 4-bit output nibble.
 4. The code translation system of claim 3 in which the translation of said first and second groups takes place substantially simultaneously, and said nibbles thereby form an 8-bit output byte, the bits of which can be transmitted from said system simultaneously.
 5. The code translation system of claim 3 in which there are selected 256 valid patterns of the possible combinations of bits of the byte of said first code, which 256 patterns define the permissible characters of said second code, and validity detection means is provided in connection with said input storage means to detect combinations in each input byte other than said 256 valid combinations.
 6. The code translation system of claim 5 in which 7 selected bits of said first group of 8 bits of an input byte there can be only 1 valid bit in each byte, and said validity detection means will detect the presence of more than 1 such bit in a byte.
 7. The code translation system of claim 5 in which there is provided intermediate decoder means responsive to an output from said input storage means to translate each of the 4 bits of said second group of the input byte into one of 16 hexadecimal code bits, and means responsive to an output from said intermediate decoder means to translate said 16 hexadecimal code bits into the 4-bit output nibble.
 8. The code translation system of claim 7 in which in 7 selected bits of said first group of 8 bits of an input byte, there can be only 1 valid bit in each byte, and means is provided to detect the presence of more than 1 such bit in a byte.
 9. The code translation system of claim 8 in which modifying means is provided responsive to the outputs of each group of bits read out from said input storage means to modify certain of said outputs in order to make the proper conversion from the first code to the second code.
 10. A method of converting from a first 12-bit-per-byte digital code representing items of coded data into a second code having in each byte 8 bits, said method comprising: storing each byte of data coded according to said first code; reading out each entire byte from storage by predetermined signals prior to entry of the next succeeding multibit input byte into said input storage means; dividing the output from storage of each said first code byte into two groups of bits, one group containing 8 bits and the other group 4 bits; separately translating the bits of each said group into a 4-bit nibble; and forming said nibbles into an output byte of said second code containing 8 bits per byte.
 11. The method of claim 10 in which said second group of 4 bits is first translated into 16 bits of a hexadecimal code, and then translated into a 4-bit nibble. 